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| Memory ICs I2C Bus compatible serial EEPROM BR24C01A / BR24C01AF / BR24C02 / BR24C02F / BR24C04 / BR24C04F **Features CMOS technology. Low power * 2.7V to 5.5V Operation. * Two wire serial interface I2C busTMcompatible. * Low power dissipation - 0.2mA (typ.) active current: 5V - 1.0A (typ.) standby current: 5V * Automatic Word Address Incrementing - Sequential register read * Automatic erase-before-write. *Pin assignments A0 A1 A2 GND 1 2 3 4 8 VCC TEST SCL SDA BR24C01A BR24C01AF BR24C02 BR24C02F 7 6 5 *Pin descriptions Pin name A0, A1, A2 Function Slave address setting pin Serial data clock Serial data input / output GND connection Power supply Ground SCL SDA TEST VCC GND * Page write buffer for up to 4 bytes: BR24C01A / AF up to 4 bytes: BR24C02 / F up to 16 bytes: BR24C04 / F * DATA security -Inhibit to write at low VCC. * Noise filters at SCL and SDA pins. * 8-pin DIP / 8-pin SOP packages. * 100,000 ERASE / WRITE cycles. * 10 years Data Retention. *Pin assignments A0 (NC) A1 A2 GND 1 2 3 4 8 7 Vcc TEST SCL SDA BR24C04 BR24C04F 6 5 *Pin descriptions Pin name Function N.C. Slave address setting pin Serial data clock Serial data input / output GND connection Power supply Ground A0 A1, A2 SCL SDA TEST VCC GND 1 Memory ICs BR24C01A / BR24C01AF / BR24C02 / BR24C02F / BR24C04 / BR24C04F *Over view / AF, BR24C02 / F, and BR24C04 / F are 2-wire serial EEPROMs which are electrically programmable. The BR24C01A The configurations are as follows: BR24C01A / AF: 128 x 8 bit 1K serial EEPROM BR24C02 / F: 256 x 8 bit 2K serial EEPROM BR24C04 / F: 512 x 8 bit 4K serial EEPROM *Block diagram BR24C01A / AF 1024 bit EEPROM array A0 A1 A2 7bit 8bit 7bit TEST SCL SDA Address decoder Slave / word address register STOP Data register START Control circuit High-voltage generator Power supply voltage detector ACK BR24C02 / F 2048 bit EEPROM array A0 A1 A2 8bit 8bit 8bit TEST SCL SDA Address decoder Slave / word address register STOP Data register START Control circuit High-voltage generator Power supply voltage detector ACK BR24C04 / F 4096 bit EEPROM array A0 (NC) A1 A2 9bit 8bit 9bit TEST SCL SDA Address decoder Slave / word address register STOP Data register START Control circuit High-voltage generator Power supply voltage detector ACK 2 Memory ICs BR24C01A / BR24C01AF / BR24C02 / BR24C02F / BR24C04 / BR24C04F *Absolute maximum ratings (Ta = 25C) Parameter Applied voltage Power dissipation Storage temperature Operating temperature Input voltage Symbol VCC Pd Tstg Topr -- Limits - 0.3 ~ + 6.5 DIP8 pin SOP8 pin 5001 3502 Unit V mW C C V - 65 ~ + 125 - 40 ~ + 85 - 0.3 ~ VCC + 0.3 1 Reduced by 5.0mW for each increase in Ta of 1C over 25C. 2 Reduced by 3.5mW for each increase in Ta of 1C over 25C. *Recommended operating conditions (Ta = 25C) Parameter Power supply voltage Input voltage Symbol VCC VIN Limits 2.7 ~ 5.5 (WRITE) 2.7 ~ 5.5 (READ) 0 ~ VCC Unit V V V *Electrical characteristics otherwise noted, Ta = - 40 to + 85C, VCC = 2.7 to 5.5V) DC characteristics (unless Parameter Input high level voltage Input low level voltage Output low level voltage Input leakage current Output leakage current Operating current dissipation Standby current SCL frequency Symbol VIH VIL VOL ILI ILO ICC ISB fSCL Min. 0.7VCC -- -- - 10 - 10 -- -- -- Typ. -- -- -- -- -- -- -- -- Max. -- 0.3VCC 0.4 10 10 1.0 2.0 100 Unit V V V A A mA A kHZ IOL = 3.0mA (SDA) VIN = 0V VCC VOUT = 0V VCC VCC = 5.5V, fSCL = 100kHz VCC = 5.5V, SDA * SCL = VCC -- Conditions -- -- 3 Memory ICs BR24C01A / BR24C01AF / BR24C02 / BR24C02F / BR24C04 / BR24C04F Operating timing characteristics (unless otherwise noted, Ta = - 40 to + 85C, VCC = 2.7 to 5.5V) Parameter Data clock HIGH time Data clock LOW time SDA / SCL rise time SDA / SCL fall time Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition setup time Bus open time before start of transfer Internal write cycle time 1 2 Symbol tHIGH tLOW tR tF tHD: STA tSU: STA tHD: DAT tSU: DAT tPD tDH tSU: STO tBUF tWR1 tWR2 tI Min. 4.0 4.7 -- -- 4.0 4.7 0 250 0.3 0.3 4.7 4.7 -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- 1.0 0.3 -- -- -- -- 3.5 -- -- -- 10 25 0.1 Unit s s s s s s ns ns s s s s ms ms s Noise erase valid time (SCL / SDA pins) 1 VCC = 4.5 to 5.5V 2 VCC = 2.7 to 4.5V Not designed for radiation resistance. 4 Memory ICs BR24C01A / BR24C01AF / BR24C02 / BR24C02F / BR24C04 / BR24C04F *Timing charts tR SCL tHD: STA tSU: DAT SDA (input) tBUF SDA (output) tPD tDH tLOW tHD: DAT tF tHIGH SCL tSU: STA SDA tHD: STA tSU: STO START BIT STOP BIT * Data is read on the rising edge of SCL. * Data is output in synchronization with the falling edge of SCL. Fig.1 Synchronized data input / output timing SCL SDA D0 Write data (n address) ACK tWR Stop condition Start condition Fig.2 Write cycle timing 5 Memory ICs operation *Circuit condition (recognition of start bit) (1) Start Before executing any command, when SCL is HIGH, a start condition (start bit) is required to cause SDA to fall from HIGH to LOW. This IC is designed to constantly detect whether there is a start condition (start bit) for the SDA and SCL line, and no commands will be executed unless this condition is satisfied. (See Figure 1 for the synchronized data input / output timing.) (2) Stop condition (recognition of stop bit) To stop any command, a stop condition (stop bit) is required. A stop condition is achieved when SDA goes from LOW to HIGH while SCL is HIGH. This enables commands to be completed. (See Figure 1 for the synchronized data input / output timing.) (3) Precautions concerning write commands In the WRITE mode, the transferred data is not written to the memory unless the stop bit is executed. (4) Device addressing With the BR24C01A / AF and BR24C02 / F Make sure the slave address is output from the master immediately after the start condition. The upper four bits of the slave address are used to determine the device type. The device code for this IC is fixed at "1010". The next three bits of the slave address (A2, A1, A0 *** device address) are used to select the device. This IC can address up to eight devices on the same bus. The lowermost bit of the slave address (R / W *** READ / WRITE) is used to set the write or read mode as follows. R / W set to 0 *** Write (Random read word address setting is also 0) R / W set to 1 *** Read 1010 A2 A1 A0 R/W BR24C01A / BR24C01AF / BR24C02 / BR24C02F / BR24C04 / BR24C04F With the BR24C04 / F Make sure the slave address is output from the master in continuation with the start condition. The upper four bits of the slave address are used to determine the device type. The device code for this IC is fixed at "1010". The next two bits of the slave address (A2, A1 *** device address) are used to select the device. This IC can address up to four devices on the same bus. The next bit of the slave address (PS *** Page Select) is used to select the page. As shown below, it can write to or read from any of the 256 words in the two pages in memory. PS set to 0 *** Page 1 (000 to 0FF) PS set to 1 *** Page 2 (100 to 1FF) The lowermost bit of the slave address (R / W *** READ / WRITE) is used to set the write or read mode as follows. R / W set to 0 *** Write (Random read word address setting is also 0) R / W set to 1 *** Read 1010 A2 A1 PS R/W 6 Memory ICs (5) ACK signal The acknowledge signal (ACK signal) is determined by software and is used to indicate whether or not a data transfer is proceeding normally. The transmitting device, whether the master or slave, opens the bus after an 8-bit data output (-COM when a write or read command of the slave address input; this IC when reading data). For the receiving device during the ninth clock cycle, SDA is set to LOW and an acknowledge signal (ACK signal) is sent to indicate that it received the 8-bit data (this IC when a write command or a read command of the slave address input, -COM when a read command data output). This IC outputs a LOW acknowledge signal (ACK signal) after recognizing the start condition and slave address (8 bits). BR24C01A / BR24C01AF / BR24C02 / BR24C02F / BR24C04 / BR24C04F When data is being written to this IC, a LOW acknowledge signal (ACK signal) is output after the receipt of each eight bits of data (word address and write data). When data is being read from the IC, eight bits of data (read data) are output and the IC waits for a returned LOW acknowledge signal (ACK signal). When an acknowledge signal (ACK signal) is detected and a stop condition is not sent from the master (-COM) side, the IC continues to output data. If an acknowledge signal (ACK signal) is not detected, the IC interrupts the data transfer and ceases reading operations after recognizing the stop condition (stop bit). The IC then enters the waiting or standby state. (See Figure 3 for acknowledge signal (ACK signal) response.) Start condition (start bit) SCL (from -COM) SDA (-COM output data) 1 8 9 SDA (BR24C01A / AF, BR24C02 / F, BR24C04 / F output data) Acknowledge signal (ACK signal) Fig.3 Acknowledge (ACK signal) response (during write and read slave address input) 7 Memory ICs (6) Byte write Start condition 1 SCL 8 9 BR24C01A / BR24C01AF / BR24C02 / BR24C02F / BR24C04 / BR24C04F Stop condition 17 18 26 27 SDA 1 0 1 0 A2 A1 A0 0 WA6 Word address WA0 D7 Write data D0 Slave address ACK signal (output) Fig.4 Byte write cycle (BR24C01A / AF) Start condition 1 SCL 8 9 17 18 26 27 Stop condition SDA 1 0 1 0 A2 A1 A0 0 WA7 WA6 Word address WA0 D7 Write data D0 Slave address ACK signal (output) Fig.5 Byte write cycle (BR24C02 / F) Start condition 1 SCL 8 9 17 18 26 27 Stop condition SDA 1 0 1 0 A2 A1 PS 0 WA7 WA6 Word address WA0 D7 Write data D0 Slave address ACK signal (output) Fig.6 Byte write cycle (BR24C04 / F) * Data is written to the address designated by the word address (n address). * After eight bits of data are input, the data is written to the memory cell by issuing the stop bit. 8 Memory ICs (7) Page write cycle BR24C01A / AF Start condition SCL BR24C01A / BR24C01AF / BR24C02 / BR24C02F / BR24C04 / BR24C04F Stop condition SDA 1 0 1 0 A2 A1 A0 0 WA6 WA0 D7 D0 D7 D0 Slave address Word address (n) Write data (n) Write data (n + 3) ACK signal (output) Fig.7 * A 4-byte write is possible using this command. * The page write command arbitrarily sets the upper five bits (WA6 to WA2) of the word address. The lower two bits (WA1 and WA0) can write up to four bytes of data with the address being incremented internally. BR24C02 / F Start condition 9 SCL 18 27 Stop condition 54 SDA 1 0 1 0 A2 A1 A0 0 WA7 WA0 D7 Write data n D0 D7 D0 Slave address Word address Write data n + 3 ACK signal (output) Fig.8 * A 4-byte write is possible using this command. * The page write command arbitrarily sets the upper six bits (WA7 to WA2) of the word address. The lower two bits (WA1 and WA0) can write up to four bytes of data with the address being incremented internally. BR24C04 / F Start condition Stop condition SCL SDA 1 0 1 0 A2 A1 PS 0 WA7 WA0 D7 Write data n D0 D7 D0 Slave address Word address Write data n + 15 ACK signal (output) Fig.9 * A 16-byte write is possible using this command. * The page write command arbitrarily sets the upper four bits (WA7 to WA4) of the word address. The lower four bits (WA3 to WA0) can write up to 16 bytes of data with the address being incremented internally. 9 Memory ICs (8) Current read Start condition BR24C01A / BR24C01AF / BR24C02 / BR24C02F / BR24C04 / BR24C04F Stop condition SCL 1 8 9 18 SDA 1 0 1 0 A2 A1 A0 1 D7 D6 D5 D2 D1 D0 1 Slave address ACK signal (output) Read data ACK signal (input) Fig.10 Current read cycle (BR24C01A / AF) Start condition Stop condition SCL 1 8 9 18 SDA 1 0 1 0 A2 A1 A0 1 D7 D6 D5 D2 D1 D0 1 Slave address ACK signal (output) Read data ACK signal (input) Fig.11 Current read cycle (BR24C02 / F) Start condition Stop condition SCL 1 8 9 18 SDA 1 0 1 0 A2 A1 PS 1 D7 D6 D5 D2 D1 D0 1 Slave address ACK signal (output) Read data ACK signal (input) Fig.12 Current read cycle (BR24C04 / F) * This IC increments the address by one position by using the internal circuit address count. It records the final word address (n address) of the executed write - read command. * This command reads the data of the next word address (n + 1 address) of the final write word address after the execution of the previous command. * When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (-COM), the next word address data can be read. [All words all read enabled] (See Figures 16 to 18 for the sequential read cycles.) * This command is ended by inputting HIGH to the ACK signal after D0 and raising the SDA signal (stop condition) by setting SCL to HIGH. 10 Memory ICs (9) Random read Start condition BR24C01A / BR24C01AF / BR24C02 / BR24C02F / BR24C04 / BR24C04F Start condition Stop condition SCL SDA 1 0 1 0 A2 A1 A0 0 WA6 Word address (add. h) WA0 1 0 1 0 A2 A1 A0 1 D7 D0 1 Slave address Slave address ACK signal (output) ACK signal (input) Read data (add. h) Fig.13 Random read cycle (BR24C01A / AF) Start condition Start condition Stop condition SCL SDA 1 0 1 0 A2 A1 A0 0 WA7 WA0 1 0 1 0 A2 A1 A0 1 D7 D0 1 Slave address Word address Slave address ACK signal (output) Read data ACK signal (input) Fig.14 Random read cycle (BR24C02 / F) Start condition Start condition Stop condition SCL SDA 1 0 1 0 A2 A1 PS 0 WA7 WA0 1 0 1 0 A2 A1 PS 1 D7 D0 1 Slave address Word address Slave address ACK signal (output) Read data ACK signal (input) Fig.15 Random read cycle (BR24C04 / F) * This command can read the designated word address data. * When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (-COM), the next word address data can be read. [All words all read enabled] (See Figures 16 to 18 for the sequential read cycles.) * This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) by raising SCL to HIGH. 11 Memory ICs (10) Sequential read Start condition BR24C01A / BR24C01AF / BR24C02 / BR24C02F / BR24C04 / BR24C04F Stop condition SCL SDA 1 0 1 0 A2 A1 A0 1 D7 Red data n D0 D7 D0 Slave address Read data n + a ACK signal (input) ACK signal (output) Fig.16 Sequential read cycle (BR24C01A / AF) (Example: For a current read) Start condition Stop condition SCL SDA 1 0 1 0 A2 A1 A0 1 D7 Red data n D0 D7 D0 Slave address Read data n + a ACK signal (input) ACK signal (output) Fig.17 Sequential read cycle (BR24C02 / F) (Example: For a current read) Start condition Stop condition SCL SDA 1 0 1 0 A2 A1 PS 1 D7 Red data n D0 D7 D0 1 Slave address Read data n + a ACK signal (input) ACK signal (output) Fig.18 Sequential read cycle (BR24C04 / F) (Example: For a current read) * When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (-COM), the next word address data can be read. [All words can be read] * This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) using the SCL signal HIGH. * Sequential reading can also be done with a random read. 12 Memory ICs BR24C01A / BR24C01AF / BR24C02 / BR24C02F / BR24C04 / BR24C04F *Operation notesrise (1) During power During power rise, the VCC may rise passing through the low voltage domain in which the IC internal circuit does not work. For this reason, there is a risk of misoperation when the power rises without full IC internal reset. To prevent this, pay attention to the following points during a power rise. 1) Set SCL = SDA = "HIGH" 2) Raise the power so as to activate the Power On Reset (P. O. R) circuit. Follow the steps below as to operate the P. O. R. circuit properly. 1) Set the power rise time (tR) to within 10ms. 2) Set the OFF domain for once power has been cut to 100ms minimum. VCC tR tOFF (2) SDA terminal pull-up resistance The SDA terminal is an open drain output. Consequently, it requires an external pull-up resistance. The appropriate pull-up resistace value is selected from the IC VOL-IOL features, which have been appended as measuring data, as well as VIL and ILI and other personal icons that control the IC in question. Recommended values 2.0k to 10k VOL--IOL features (Note: Typ.) 20 18 OUTPUT CURRENT: IOL (mA) OUTPUT CURRENT: IOL (mA) VOL--IOL features (Note: Typ.) 20 18 16 14 12 10 8 6 4 2 16 14 12 10 8 6 4 2 0 0.1 0.2 0.3 VCC = 5.0V Ta = 25 0.4 VCC = 4.5V 0.5 VCC = 5.5V Ta = - 40 0 VCC = 2.7V 0.1 0.2 0.3 VCC = 3.0V Ta = 25 0.4 VCC = 2.7V 0.5 VCC = 3.3V Ta = - 40 VCC = 4.5V VCC = 5.5V Ta = 85 VCC = 3.3V Ta = 85 OUTPUT VOLTAGE: VOL (V) Note: All memory array data are set to "FF" status at time of shipping. *External dimensions (Units: mm) 9.3 0.3 6.5 0.3 8 5 5.0 0.2 8 6.2 0.3 4.4 0.2 5 0.51Min. 7.62 3.2 0.2 3.4 0.3 1.5 0.1 1 4 0.3 0.1 0.11 1.27 0.4 0.1 0.3Min. 0.15 2.54 0.5 0.1 0 ~ 15 DIP8 SOP8 0.15 0.1 1 4 13 |
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